The present invention relates to a semiconductor device and TO a technique for use in the manufacture thereof, and, more particularly, the invention relates to a technique which is applicable to a semiconductor device having a plurality of semiconductor chips mounted on a mounting substrate thereof.
With an aim toward realization of multi-functioning, high integration and miniaturization of a semiconductor device, there has been proposed a stacked package in which a plurality of semiconductor chips are three-dimensionally mounted on a mounting substrate. Further, in some memory products or the like, for the purpose of obtaining high integration, a plurality of the same semiconductor chips are stacked.
For example, in the following patent literatures 1 or 2, a chip-stacking-type package element, in which semiconductor IC elements having a same size are stacked, and a manufacturing method thereof are disclosed.
[Patent Literature 1]
Japanese Unexamined Patent Publication 2003-78106 (FIG. 1)
[Patent Literature 2]
Japanese Unexamined Patent Publication Hei 6(1994)-244360 (FIG. 1)